How IBM is training AI to explain VHDL code for high-performance chip design

IBM’s quest to make AI understand VHDL

Designing high-performance microprocessors is a notoriously complex task, requiring deep expertise in hardware description languages like VHDL. While AI has made inroads into chip design—particularly with Verilog—VHDL has remained relatively untouched by large language models (LLMs). That’s changing now, thanks to a team at IBM Research, which has developed a customized LLM specifically for explaining VHDL code, a critical step in onboarding new engineers and preserving institutional knowledge.

Why VHDL matters

VHDL (VHSIC Hardware Description Language) is widely used in industries like aerospace, automotive, and high-performance computing. Unlike Verilog, which has seen more AI adoption, VHDL’s strong typing and deterministic concurrency modeling make it a preferred choice for complex microprocessor designs. However, the scarcity of VHDL expertise poses a major bottleneck in chip development. IBM’s solution? Train an AI assistant that can decode legacy VHDL code and help engineers understand decades-old designs.

The challenges of training an industrial-grade AI model

Building an LLM for proprietary chip design isn’t as simple as fine-tuning an off-the-shelf model. IBM faced several hurdles:

1. Security: Chip designs are highly confidential, requiring all training and inference to happen in secure, isolated environments.
2. Data scarcity: VHDL expertise is rare, and high-quality training data—such as internal documentation, architecture specs, and expert-written explanations—is scattered across unstructured sources.
3. Evaluation bottlenecks: Subject-matter experts (SMEs) are in short supply, making manual model evaluation slow and expensive.

To overcome these challenges, IBM built a secure cloud infrastructure with strict access controls and developed automated pipelines to preprocess internal documents, GitHub repositories, and educational materials into training data.

How IBM trained its VHDL expert

The team started with Granite, IBM’s open-source code foundation model, and extended its pretraining with 162 million tokens of VHDL and proprietary variants, alongside other hardware-related documents. To prevent catastrophic forgetting (where the model loses general coding knowledge), they mixed in 168 million tokens of other programming languages.

Key training insights:

• Data balance matters: Too much replay data (from the base model’s training set) slowed new learning, while too much code (vs. documents) hurt knowledge retention.
• Instruction tuning boosts performance: After pretraining, the model was fine-tuned on 1.1 million instruction-following examples, improving its ability to generate concise, accurate explanations.

Testing the AI’s VHDL knowledge

IBM created two test sets:

1. Code Explanation: 80 snippets of VHDL with expert-written reference explanations.
2. Multiple-Choice: 263 questions on digital design, microarchitecture, and VHDL syntax.

Human experts rated the AI’s explanations on correctness, completeness, compactness, and consistency. The base model scored just 43%, but after extended pretraining (EPT), performance jumped to 69%. Further instruction tuning pushed it to 71%—close to human-level understanding.

Automating evaluation with AI judges

With SMEs in short supply, IBM experimented with LLM-as-a-judge, using three different models to score explanations. The best AI judge (Judge 2) correlated 0.95 with human ratings, allowing faster iteration.

The future: AI that rivals human experts

Newer foundation models with better reasoning capabilities could push performance even higher. Early tests suggest an upcoming 14B-parameter model could achieve 85% accuracy—potentially surpassing human experts in consistency.

Why this matters for chip design

High-performance processor design cycles are long and labor-intensive. AI assistants that can explain, debug, and even generate VHDL could drastically accelerate development. IBM’s work is a major step toward AI-augmented hardware engineering—where LLMs don’t just write code but help preserve and disseminate decades of institutional knowledge.

What’s next?

IBM plans to:

• Expand the model’s capabilities to debugging and verification.
• Incorporate newer reasoning-focused LLMs.
• Deploy the assistant more widely within their chip design teams.

As AI continues to evolve, we may soon see models that don’t just assist engineers but actively collaborate in designing the next generation of microprocessors.